MSL Moisture Sensitivity Level Preconditioning
MSL : To evaluate the risk of component damage during soldering caused by moisture absorption.
Preconditioning : Preconditioning for conducting reliability testing.
<To be provided at the time of request>
・Sample information (quantity, package outline drawing(POD), etc.)
・Test details and conditions
・Standards ▶JESD22-A113, J-STD-020, etc.
・Pre-reflow confirmation samples (minimum of 3)
Test details for reference:
THB Temperature Humidity Bias
HAST Biased HAST
<Purpose>
To evaluate humidity-induced corrosion and degradation under high temperature and humidity while applying bias voltage.
<To be provided at the time of request>
・Sample information (quantity, package outline drawing(POD), etc.)
・Test conditions
・Standards ▶ JESD22-A101, JESD22-A110, etc.
・Test board (THB board)
・Socket
Test details for reference:
UHAST Unbiased HAST
<Purpose>
To evaluate the effects on material degradation, performance changes, and lifetime under high-temperature conditions.
<To be provided at the time of request>
・Sample information (quantity, package outline drawing(POD), etc.)
・Test conditions
・Standards ▶ JESD22-A118, etc.
Test details for reference:
TC Temperature Cycle
<Purpose>
To evaluate material fatigue and degradation caused by expansion and contraction under repeated high and low temperature cycling.
<To be provided at the time of request>
・Sample information (quantity, package outline drawing(POD), etc.)
・Test conditions
・Standards ▶ JESD22-A104, etc.
Test details for reference:
ELFR Early Failure Rate
<Purpose>
To operate components in a high-temperature environment and accelerate early failure.
<To be provided at the time of request>
・Sample information (quantity, package outline drawing (POD), etc.)
・Test conditions
・Standards ▶ AEC-Q100-008, etc.
・Test board (Burn-in Board)
・Socket
・Input signal
Test details for reference:
HTOL High Temperature Operating Life
LTOL Low Temperature Operating Life
<Purpose>
To operate components in high (low) temperatures and accelerate potential failure modes.
<To be provided at the time of request>
・Sample information (quantity, package outline drawing (POD), etc.)
・Test conditions
・Standards ▶ JESD22-A108, etc.
・Test board (Burn-in Board)
・Socket
・Input signal
Test details for reference:
ESD Electrostatic Discharge
<Purpose>
To evaluate the product’s ability to withstand electrostatic damage.
<To be provided at the time of request>
・Sample information (quantity, package outline drawing (POD), etc.)
・Pin information (type, withstand voltage, etc.)
・Test conditions
・Standards ▶ AEC-Q100-002, AEC-Q100-011, AEC-Q100-003, etc.
(・Test board) *When a universal test board cannot be used
Test details for reference:
LU Latch-up
<Purpose>
To evaluate latch-up immunity.
*Latch-up is a phenomenon in CMOS devices where a parasitic thyristor structure is inadvertently triggered by external stress, resulting in continuing excessive current flow.
<To be provided at the time of request>
・Sample information (quantity, package outline drawing (POD), etc.)
・Pin information (type, withstand voltage, etc.)
・Test conditions
・Standards ▶ AEC-Q100-004, etc.
(・Test board) **When a universal test board cannot be used
Test details for reference:
